At present, a test circuit integrated into a memory and an associated test algorithm, known to the person skilled in the art as a built-in self-test (BIST) algorithm, write dedicated test words into the memory array on command and then extract them and compare the test bits of the extracted words with the expected binary data bits. This necessitates the use of decoder logic which is connected to the output of the memory array and also receives the expected data, whose overall size increases as the width of the data bus of the memory increases, i.e. as the number of bits of the test words increases.
Also, in addition to this penalizing aspect of the overall surface area, this kind of decoder logic causes substantial problems with the hardware implementation (“routability”) of the connections between the components of the decoder logic.